1. Field of Invention
The present invention relates to a silicon-on-insulator device structure. More particularly, the present invention relates to a silicon-on-insulator metallic oxide semiconductor (MOS) structure.
2. Description of Related Art
Silicon-on-insulator (SOI) structure is a technique for isolating complementary MOS (CMOS) transistors from a substrate. The principle is to establish a layer of insulating material (in general a silicon dioxide layer) not far away from the surface of a silicon substrate, thereby isolating a layer of substrate silicon from the main substrate body below. A CMOS transistor can then be fabricated on the isolated substrate silicon layer above the insulating layer, and hence the structure is called silicon-on-insulator. Since the area for fabricating the CMOS transistor is isolated from the substrate main body, certain conventional latch-up paths will be excluded. For example, conventional latch-up paths such as "source terminal to the substrate" and "well region to the substrate" no longer exist due to the isolation provided by this insulating layer.
The SOI structure can be fabricated using isolation by implanted oxygen (SIMOX) method, bonded wafer method or dielectric isolation (DI) method. The advantages of having a SOI structure, other than being capable of reducing parasitic bipolar effects of a CMOS transistor, include the ability to increase its immunity to soft errors caused by powerful .alpha.-particles. Furthermore, since the permitted line width is smaller, the level of integration can be increased. In addition, since the number of masks necessary for fabricating a device for a SOI structure is fewer, the manufacturing process is very much simplified. The reduction of parasitic bipolar effects together with the reduction of device dimensions further boost the operational speed of the circuit.
FIG. 1 is a cross-sectional view showing a MOS device on a conventional silicon-on-insulator structure. The method of fabrication includes the steps of first defining an active device region out of a silicon main body 100 by a device isolating structure 102. Then, a buried oxide layer 104 is formed in the silicon main body 100. Next, a P-type silicon substrate 100a is formed above the buried oxide layer 104, and then a gate terminal 106, for example, of a MOS transistor, is formed above the P-type silicon substrate 100a. Finally, N-type source region 108a and drain region 108b are formed on each side of the gate terminal 106.
In the aforementioned SOI device, the P-type silicon substrate 100a is in a floating state. Therefore, unwanted current can easily flow between the drain region 108b and the source region 108a due to the transfer of electrons at the interface between the source region 108a and the P-type silicon substrate 100a. This is the so-called floating body effect, and will affect the functionality of the device as well as lowering its reliability. Hence, a tie down voltage is often connected to the P-type silicon substrate 100a in order to reduce the floating body effect. However, part of the SOI device area is usually sacrificed for each of the methods for connecting with the P-type silicon substrate 100a. FIG. 2 is a top view showing the structural layout of a conventional SOI device. As shown in FIG. 2, a source region 202a and a drain region 206b are formed on each side of a gate terminal 200. To connect the P-type silicon substrate 100a as shown in FIG. 1 to a tie down voltage, an extension area 204 is needed above the SOI device region as shown in FIG. 2. Furthermore, there is a contact window 206 above the extension area 204 for supplying the necessary low tie down voltage to the P-type silicon substrate 100a. This extension area 204, however occupies useful device space, thereby lowering the level of device integration. This is a highly undesirably state of affair in the fabrication of integrated circuits.
In light of the foregoing, there is a need to improve the conventional method of fabricating a SOI device.